Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
A method for generating weighted random test pattern
IBM Journal of Research and Development
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Techniques for estimating test length under random test
Journal of Electronic Testing: Theory and Applications - Special issue on economics of electronic design, manufacture and test
Concrete Math
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Instruction Randomization Self Test For Processor Cores
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
STAR-ATPG: A High Speed Test Pattern Generator for Large Scan Designs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST
IEEE Transactions on Computers
International Journal of High Performance Computing Applications
Power problems in VLSI circuit testing
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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Two problems in weighted random pattern testing are considered: 1) evaluating a set of input weights in terms of the amount of time required to generate a set of test patterns and 2) determining the optimal weights for a given test set. An exact expression for expected test length is derived as a function of input weights. Upper and lower bounds for expected test length are presented. Percentage error of approximation is expressed in terms of the bounds. Based on these results, algorithms are given for approximating expected test length. These algorithms allow the user to tradeoff accuracy and computational complexity. Experiments with some test sets are presented to illustrate the accuracy of the approximation technique. Expected test length is shown to be a convex function of input weights. A simple hill-climbing algorithm is defined to find optimal weights for a given set of test patterns. When hardware constraints, limiting the number of weights to be realized for each input bit, are also specified, a simple modification of the algorithm suffices in yielding optimal weights in the constrained space. Experiments with several circuits yield of the order of 96% to 99% reduction in expected test length over that achieved by current techniques.