Characterization and Implicit Identification of Sequential Indistinguishability
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Implication and Evaluation Techniques for Proving Fault Equivalence
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
COMBINATIONAL LOGIC SYNTHESIS FOR DIVERSITY IN DUPLEX SYSTEMS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Random Pattern Fault Simulation in Multi-Valued Circuits
ISMVL '95 Proceedings of the 25th International Symposium on Multiple-Valued Logic
A Design Diversity Metric and Reliability Analysis for Redundant Systems
ITC '99 Proceedings of the 1999 IEEE International Test Conference
STAR-ATPG: A High Speed Test Pattern Generator for Large Scan Designs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Design of Totally Fault Locatable Combinational Networks
IEEE Transactions on Computers
Design for Testability A Survey
IEEE Transactions on Computers
Use of SPOOF's in the Analysis of Faulty Logic Networks
IEEE Transactions on Computers
Multiple Fault Detection in Combinational Circuits: Algorithms and Computational Results
IEEE Transactions on Computers
Sequential Fault Diagnosis in Combinational Networks
IEEE Transactions on Computers
Generic Fault Characterizations for Table Look-Up Coverage Bounding
IEEE Transactions on Computers
Boolean Differential Calculus and its Application to Switching Theory
IEEE Transactions on Computers
Fault Masking in Combinational Logic Circuits
IEEE Transactions on Computers
Reliability Modeling of Compensating Module Failures in Majority Voted Redundancy
IEEE Transactions on Computers
The Probability of a Correct Output from a Combinational Circuit
IEEE Transactions on Computers
A Combinatorial Solution to the Reliability of Interwoven Redundant Logic Networks
IEEE Transactions on Computers
An On-Line Algorithm for the Location of Cross Point Faults in Programmable Logic Arrays
IEEE Transactions on Computers
Strongly Fault Secure Logic Networks
IEEE Transactions on Computers
Properties of Faults and Criticalities of Values under Tests for Combinational Networks
IEEE Transactions on Computers
Identification of Equivalent Faults in Logic Networks
IEEE Transactions on Computers
Multiple Fault Testing of Large Circuits by Single Fault Test Sets
IEEE Transactions on Computers
Resolution-Oriented Fault Interrelationships in Combinational Logic Networks
IEEE Transactions on Computers
Algebraic Properties of Functions Affecting Optimum Fault-Tolerant Realizations
IEEE Transactions on Computers
Fault Diagnosis in Combinational Tree Networks
IEEE Transactions on Computers
Fault Diagnosis in Synchronous Sequential Circuits Based on an Effect-Cause Analysis
IEEE Transactions on Computers
Identification of Multiple Stuck-Type Faults in Combinational Networks
IEEE Transactions on Computers
Circuit Structure and Switching Function Verification
IEEE Transactions on Computers
A New Representation for Faults in Combinational Digital Circuits
IEEE Transactions on Computers
An analysis of the multiple fault detection capabilities of single stuck-at fault test sets
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
LSI logic testing: an overview
IEEE Transactions on Computers
Quantitative evaluation of soft error injection techniques for robust system design
Proceedings of the 50th Annual Design Automation Conference
| Hi-index | 15.05 |
This paper is a study of the effects of faults on the logical operation of combinational (acyclic) logic circuits. In particular, the conditions whereby two different faults can produce the same alteration in the circuit behavior are investigated. This relationship between two faults is shown to be an equivalence relation, and three different types of equivalence relations are specified. Necessary and sufficient conditions for the existence of these equivalence relations are proved. An algorithm for determining the equivalence classes for one of the types of equivalence is presented. Other types of algebraic properties of faults are discussed.