The Fanout Structure of Switching Functions
Journal of the ACM (JACM)
Partitioning logic circuits to maximize fault resolution
DAC '76 Proceedings of the 13th Design Automation Conference
Design of Totally Fault Locatable Combinational Networks
IEEE Transactions on Computers
Polynomially Complete Fault Detection Problems
IEEE Transactions on Computers
Use of SPOOF's in the Analysis of Faulty Logic Networks
IEEE Transactions on Computers
Diagnosis and Fault Equivalence in Combinational Circuits
IEEE Transactions on Computers
Fault Equivalence in Combinational Logic Networks
IEEE Transactions on Computers
On Realizations of Boolean Functions Requiring a Minimal or Near-Minimal Number of Tests
IEEE Transactions on Computers
A New Representation for Faults in Combinational Digital Circuits
IEEE Transactions on Computers
General Criterion for Essential Nonfault Locatability of Logical Functions
IEEE Transactions on Computers
Characterization and Implicit Identification of Sequential Indistinguishability
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Implication and Evaluation Techniques for Proving Fault Equivalence
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
| Hi-index | 14.98 |
The properties of combinational logic functions and networks that influence equivalence among stuck-type faults are investigated. It is shown that the equivalence of certain types of faults depends only on the function being realized. For instance, the fault classes among primary input/output faults are of this type. It is shown that every irredundant realization of the two-variable EXCLUSIVE-OR function has a unique set of ten fault classes. A fault class F in a module M contained in a network N is called intrinsic, if F can be determined from M alone, i. e., F is independent of N. Using the concepts of intrinsic equivalence and inversion parity, conditions for the equivalence and nonequivalence of two fault classes are obtained. These results are applied to the problem of equivalence identification in two-level logic networks where they provide a substantial reduction in the amount of computation required.