Implication and Evaluation Techniques for Proving Fault Equivalence

Authors:
M. Enamul Amyeen;W. Kent Fuchs;Irith Pomeranz;Vamsi Boppana
Affiliations:
-;-;-;-
Venue:
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Year:
1999

Citing 12
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Abstract

Efficient identification of fault equivalence is essential for the completeness and efficiency of diagnostic test pattern generation. In this paper, we present new techniques to prove diagnostic fault equivalence. The techniques are based on implication of the faulty values, and functional evaluation at the dominator gate of the fault sites. The experimental results for all ISCAS85 circuits and full scan versions of ISCAS89 circuits show significant improvement compared to previously proposed techniques in both the number of equivalent pairs identified and the time to prove equivalence.