Checkpoint Faults are not Sufficient Target Faults for Test Generation
IEEE Transactions on Computers
A topological search algorithm for ATPG
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Characterization and Implicit Identification of Sequential Indistinguishability
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Implication and Evaluation Techniques for Proving Fault Equivalence
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Diagnostic and Detection Fault Collapsing for Multiple Output Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Evaluation of Collapsing Methods for Fault Diagnosis
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Theorems for Fault Collapsing in Combinational Circuits
Journal of Electronic Testing: Theory and Applications
Bilateral Testing of Nano-scale Fault-Tolerant Circuits
Journal of Electronic Testing: Theory and Applications
Improved diagnosis using enhanced fault dominance
Integration, the VLSI Journal
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The partitioning of faults into equivalence classes so that only one representative fault per class must be explicitly considered in fault simulation and test generation, called fault collapsing, is addressed. Two types of equivalence, which are relevant to the work reported, are summarized. New theorems on fault equivalence and dominance, forming the basis of an algorithm that collapses all the structurally equivalent faults in a circuit, plus many of the functionally equivalent faults, are presented. Application of the algorithm to a set of benchmark circuits establishes that identification of functionally equivalent faults is feasible, and that, in some cases, they are a large fraction of the faults in a circuit. The collapsing algorithm applies not only to combinational designs but to synchronous sequential circuits as well.