Logic testing and design for testability
Logic testing and design for testability
Checkpoints in irredundant two-level combinatorial circuits
Journal of Electronic Testing: Theory and Applications
Advanced Fault Collapsing (Logic Circuits Testing)
IEEE Design & Test
On the Equivalence of Fanout-Point Faults
IEEE Transactions on Computers
Diagnostic Fault Equivalence Identification Using Redundancy Information and Structural Analysis
Proceedings of the IEEE International Test Conference on Test and Design Validity
Looking for Functional Fault Equivalence
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Fanout fault analysis for digital logic circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets
ITC '02 Proceedings of the 2002 IEEE International Test Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper gives a mathematical approach to fault collapsing based on the stuck-at fault model for combinational circuits. The mathematical structure we work within is a Boolean ring of Boolean functions of several variables. The goal of fault collapsing for a given circuit is to reduce the number of stuck-at faults to be considered in test generation and fault diagnosis. For this purpose we need rules that let us eliminate faults from the considered fault set. In this paper some earlier known rules are proved in the new context, and several new rules are presented and proved. The most important of the new theorems deal with the relationship between stuck-at faults on a fanout stem and the branches. The concept of monotony of Boolean functions appears to be important in most of these new rules.