Fanout fault analysis for digital logic circuits

Authors:
J. E. Chen;Chung Len Lee;Wen Zen Shen;Beyin Chen
Affiliations:
-;-;-;-
Venue:
ATS '95 Proceedings of the 4th Asian Test Symposium
Year:
1995

Citing 3
Cited 2

Checkpoint Faults are not Sufficient Target Faults for Test Generation

IEEE Transactions on Computers
Logic Minimization Algorithms for VLSI Synthesis

Logic Minimization Algorithms for VLSI Synthesis
A New Representation for Faults in Combinational Digital Circuits

IEEE Transactions on Computers

Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption

Journal of Electronic Testing: Theory and Applications
Theorems for Fault Collapsing in Combinational Circuits

Journal of Electronic Testing: Theory and Applications

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Abstract

Conventional fault relationships are mostly restricted to faults at a gate or within a fanout free region. In this paper, we analyze the fault relationships beyond the fanout free region for general digital logic circuits. An improved fault collapsing procedure is proposed and applied to several kinds of combinational benchmark circuits and 31 sequential benchmark circuits to collapsing faults. Improvements of 2-8% for an initial set of target faults of a circuit can be obtained. For some of circuits, the reduction ratio can have up to 20% improvement. This may save a lot of time in test generation and fault simulation processes.