Logic testing and design for testability
Logic testing and design for testability
The Ballast Methodology for Structured Partial Scan Design
IEEE Transactions on Computers
Multiple fault detection in two-level multi-output circuits
Journal of Electronic Testing: Theory and Applications
Partial scan design of register-transfer level circuits
Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
A New Class of Sequential Circuits with Combinational Test Generation Complexity
IEEE Transactions on Computers
Fanout fault analysis for digital logic circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits
ATS '98 Proceedings of the 7th Asian Test Symposium
Sequential Circuits with combinational Test Generation Complexity
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
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We show that the test generation problem for all single stuck-at faults in sequential circuits with internally balanced structures can be reduced into the test generation problem for single stuck-at faults in combinational circuits. In our previous work, we introduced internally balanced structures as a class of sequential circuits with the combinational test generation complexity. However, single stuck-at faults on some primary inputs, called separable primary inputs, corresponded to multiple stuck-at faults in a transformed combinational circuit. In this paper, we resolve this problem. We show how to generate a test sequence and identify undetectability for single stuck-at faults on separable primary inputs.