Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
The Ballast Methodology for Structured Partial Scan Design
IEEE Transactions on Computers
Introduction to algorithms
An exact algorithm for selecting partial scan flip-flops
DAC '94 Proceedings of the 31st annual Design Automation Conference
Bottleneck removal algorithm for dynamic compaction and test cycles reduction
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Cost-free scan: a low-overhead scan path design methodology
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Configuring multiple scan chains for minimum test time
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Software transformations for sequential test generation
ATS '95 Proceedings of the 4th Asian Test Symposium
Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Reconfiguration techniques for a single scan chain
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A test synthesis approach to reducing BALLAST DFT overhead
DAC '97 Proceedings of the 34th annual Design Automation Conference
A New Class of Sequential Circuits with Combinational Test Generation Complexity
IEEE Transactions on Computers
Test generation for acyclic sequential circuits with hold registers
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption
Journal of Electronic Testing: Theory and Applications
Software transformations for sequential test generation
ATS '95 Proceedings of the 4th Asian Test Symposium
Combinational Test Generation for Various Classes of Acyclic Sequential Circuits
ITC '01 Proceedings of the 2001 IEEE International Test Conference
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We propose a new design for testability (DFIJ technique which, like full scan design, guarantees that tests can be derived using a combinational test generator. Our DFT technique has two important advantages overfull scan design: (1) the area overhead incurred by our technique is significantly less and (2) the test application time for our technique is significantly lower. This DFT technique selects scan flip-flops and/or test points such that, in the test mode, the circuit will belong to a special class of sequential circuits that we call as strongly balanced structures. We give a simple characterization for strongly balanced structures and provide efficient methods to select scan Rip. flops and/or test points to reduce any sequential circuit to a strongly balanced structure. A complete test set can be obtained for a strongly balanced structure using a combinational test generator. Experimental results on ISCAS 89 benchmark circuits and production VLSI circuits show that both the DFT overhead and the test application time are substantially lower for our technique.