Test generation for acyclic sequential circuits with hold registers

Authors:
Tomoo Inoue;Debesh Kumar Das;Chiiho Sano;Takahiro Mihara;Hideo Fujiwara
Affiliations:
Hiroshima City University, Hiroshima 731-3194, Japan;Jadavpur University, Calcutta- 700 032, India;Nara Institute of Science and Technology, Nara 630-0101, Japan;Mitsubishi Electronic Control Software Corporation, Kobe 652-0871, Japan;Nara Institute of Science and Technology, Nara 630-0101, Japan
Venue:
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Year:
2000

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Abstract

We present a method of test generation for acyclic sequential circuits with hold registers. A complete (100% fault efficiency) test sequence for an acyclic sequential circuit can be obtained by applying a combinational test generator to all the maximal time-expansion models (TEMs) of the circuit. We propose a class of acyclic sequential circuits for which the number of maximal TEMs is one, i.e, the maximum TEM exists. For a circuit in the class, test generation can be performed by using only the maximum TEM.The proposed class of sequential circuits with the maximum TEM properly includes several known classes of acyclic sequential circuits such as balanced structures and acyclic sequential circuits without hold registers for which test generation can be also performed by using a combinational test generator. Therefore, in general, the hardware overhead for partial scan based on the proposed structure is smaller than that based on balanced or acyclic sequential structure without hold registers.