Test generation for acyclic sequential circuits with hold registers
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits
ATS '98 Proceedings of the 7th Asian Test Symposium
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
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