An analytical approach to the partial scan problem

Generation of deterministic test patterns by minimal basic test sets

EURO-DAC '92 Proceedings of the conference on European design automation

Partial scan with retiming

DAC '93 Proceedings of the 30th international Design Automation Conference

A cost-based approach to partial scan

DAC '93 Proceedings of the 30th international Design Automation Conference

An exact algorithm for selecting partial scan flip-flops

DAC '94 Proceedings of the 31st annual Design Automation Conference

Test pattern generation hardware motivated by pseudo-exhaustive test techniques

EURO-DAC '94 Proceedings of the conference on European design automation

Testability analysis and improvement from VHDL behavioral specifications

EURO-DAC '94 Proceedings of the conference on European design automation

Partial scan selection for user-specified fault coverage

EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation

Test register insertion with minimum hardware cost

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Retiming-Based Partial Scan

IEEE Transactions on Computers

Efficient random testing with global weights

EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation

Full scan fault coverage with partial scan

DATE '99 Proceedings of the conference on Design, automation and test in Europe

Deterministic BIST with Partial Scan

Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999

Test generation for acyclic sequential circuits with hold registers

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design

Timing-Driven Partial Scan

IEEE Design & Test

Cost-Driven Ranking of Memory Elements for Partial Intrusion

IEEE Design & Test

Fault diagnosis using state information

FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)

Sequential Circuit Testing: From DFT to SFT

VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

10.1 Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

Combinational Test Generation for Various Classes of Acyclic Sequential Circuits

ITC '01 Proceedings of the 2001 IEEE International Test Conference

On the selection of a partial scan path with respect to target faults

EURO-DAC '91 Proceedings of the conference on European design automation

Partial Scan Design Based on Circuit State Information and Functional Analysis

IEEE Transactions on Computers

Configuring flip-flops to BIST registers

ITC'94 Proceedings of the 1994 international conference on Test

An O(2O(k)n3) FPT algorithm for the undirected feedback vertex set problem*

COCOON'05 Proceedings of the 11th annual international conference on Computing and Combinatorics

Eliminating the Timing Penalty of Scan

Journal of Electronic Testing: Theory and Applications