The Ballast Methodology for Structured Partial Scan Design
IEEE Transactions on Computers
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
An analytical approach to the partial scan problem
Journal of Electronic Testing: Theory and Applications
Design for testability for path delay faults in sequential circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
An exact algorithm for selecting partial scan flip-flops
Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
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We propose a novel hardware model to reconfigure a sequential ULSI circuit for partial-scanned delay-fault built-in self-test (BIST). We modify the standard stuck-fault BIST model to ensure highly robust delay tests by inserting hardware to avoid circuit hazards that invalidate delay tests. The model treats un-scanned flip-flops and latches as inverters or buffers. We propose a novel minimum feedback vertex set (FVS) algorithm based on quadratic O-1 programming (which has O(n2) complexity) for partial-scan flip-fiop selection. We obtain a pipelined sequential circuit and insert parity-flippers to remove hazards during testing. We avoid placing hardware on time-critical paths. We find the FVS and insert deglitching hardware for all of the 1989 ISCAS circuits.