A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Delay fault models and test generation for random logic sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Test generation for delay faults in non-scan and partial scan sequential circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Clock grouping: a low cost DFT methodology for delay testing
DAC '94 Proceedings of the 31st annual Design Automation Conference
Partial scan selection for user-specified fault coverage
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Generation of High Quality Tests for Robustly Untestable Path Delay Faults
IEEE Transactions on Computers
A BIST scheme for the detection of path-delay faults
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Design for high-speed testability of stuck-at faults
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
10.1 Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Detection of multiple transitions in delay fault test of SPARC64 microprocessor
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
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