A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Design for testability for path delay faults in sequential circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Robust testing for stuck-at faults
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
A graph approach to DFT hardware placement for robust delay fault BIST
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Simulation of at-speed tests for stuck-at faults
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
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When tests are applied at the maximum allowable clock frequency or the rated speed, delays of critical paths can be comparable to the clock period. Hence, delayed signal transitions or timing hazards can influence the detection of faults. It is thus possible that a stuck-at fault that is detected by a test applied at slow speed, may not be detected with high speed test application. This paper makes two new contributions. First, we present a new multivalue algebra and a comprehensive test generation algorithm for the previously described dh-robust tests for stuck-at faults. These tests guarantee fault detection at any clock speed up to the rated clock speed of the circuit even when a delay fault is also present. Second, we identify that presence of sequential feedbacks and reconvergent fanouts as the primary obstacle in obtaining the dh-robust tests for a sequential circuits. We propose cycle-free sequential circuits, which may be obtained by partial scan, if necessary, as the design for high-speed testability.