Design for testability for path delay faults in sequential circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Generation of high quality non-robust tests for path delay faults
DAC '94 Proceedings of the 31st annual Design Automation Conference
Fastpath: A Path-Delay Test Generator for Standard Scan Designs
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Testability Features of AMD-K6TM Microprocessor
Proceedings of the IEEE International Test Conference
Skewed-Load Transition Test: Part 1, Calculus
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Testing the 400-MHz IBM Generation-4 CMOS Chip
Proceedings of the IEEE International Test Conference
Skewed-Load Transition Test: Part 2, Coverage
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Too much delay fault coverage is a bad thing
Proceedings of the IEEE International Test Conference 2001
Modeling and testing the Gekko microprocessor, an IBM PowerPC derivative for Nintendo
Proceedings of the IEEE International Test Conference 2001
A Flexible Path Selection Procedure for Path Delay Fault Testing
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Selection of Potentially Testable Path Delay Faults for Test Generation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Method Evaluation Experiments & Data
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults
Proceedings of the conference on Design, automation and test in Europe
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
DFT Advances in Motorola's MPC7400, a PowerPCTM Microprocessor
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Delay defect screening for a 2.16GHz SPARC64 microprocessor
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
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This work presents a new non-robust delay fault test generation method for the purpose of screening delay defects of microprocessors with fewer test vectors. It is important to reduce the number of test vectors in order to reduce test time, memory usage in the tester, and the overall testing cost. By paying attention to the constraints of off-path inputs in a non-robust test, we made it possible to generate a pair of test vectors to detect multiple delay faults based on the traditional dynamic compaction technique. Delay fault test based on our method is applied to SPARC64 microprocessor with 1.3 GHz clock for screening delay defects, and we achieved 90% coverage with 3,567 test vectors. The comparison results also show that the robust test is not practical for the screening purpose, since it needs more than three times the number of test vectors as compared to the non-robust test.