Fast identification of robust dependent path delay faults
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Test generation for primitive path delay faults in combinational circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Fast identification of untestable delay faults using implications
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
On primitive fault test generation in non-scan sequential circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
An efficient non-enumerative method to estimate path delay fault coverage
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Efficient Identification of Non-Robustly Untestable Path Delay Faults
Proceedings of the IEEE International Test Conference
Delay Testing for Non-Robust Untestable Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
A Flexible Path Selection Procedure for Path Delay Fault Testing
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Timing analysis of computer hardware
IBM Journal of Research and Development
Primitive delay faults: identification, testing, and design for testability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Delay fault coverage, test set size, and performance trade-offs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On Selecting Testable Paths in Scan Designs
Journal of Electronic Testing: Theory and Applications
Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A Statistical Fault Coverage Metric for Realistic Path Delay Faults
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
TranGen: a SAT-based ATPG for path-oriented transition faults
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Path delay test compaction with process variation tolerance
Proceedings of the 42nd annual Design Automation Conference
Yield-Driven, False-Path-Aware Clock Skew Scheduling
IEEE Design & Test
Detection of multiple transitions in delay fault test of SPARC64 microprocessor
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A dynamic test compaction procedure for high-quality path delay testing
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
On effective criterion of path selection for delay testing
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Estimation of delay test quality and its application to test generation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Path selection for transition path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Input necessary assignments for testing of path delay faults in standard-scan circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test generation for clock-domain crossing faults in integrated circuits
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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We present a method of path selection and test generationfor path delay faults. The proposed method addresses thefact that logic circuits typically have very large numbers ofpaths, and a large percentage of these paths are typicallyuntestable. The proposed method selects a set of potentiallytestable long paths by utilizing non-enumerativeidentification of untestable paths and removing untestablepaths from consideration. Test generation is also applied aspart of the proposed method. We demonstrate the effectivenessof the method by presenting results for benchmarkcircuits.