Fast identification of untestable delay faults using implications
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Test Generation for Path Delay Faults Using Binary Decision Diagrams
IEEE Transactions on Computers
Efficient Identification of Non-Robustly Untestable Path Delay Faults
Proceedings of the IEEE International Test Conference
Selection of Potentially Testable Path Delay Faults for Test Generation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Efficient Method to Identify Untestable Path Delay Faults
ATS '01 Proceedings of the 10th Asian Test Symposium
Classification and identification of nonrobust untestable path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact path delay fault coverage with fundamental ZBDD operations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Implicit and Exact Path Delay Fault Grading in Sequential Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Low power test generation for path delay faults using stability functions
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
An Improved Method for Identifying Linear Dependencies in Path Delay Faults
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Function-based compact test pattern generation for path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present a novel framework to identify all the robustly testable and untestable path delay faults in a circuit. The method uses a combination of decision diagrams for manipulatingpath delay faults and boolean functions. The approach bene.ts from processing partial paths or fanout free segments in the circuit rather than the entire path. The effectiveness of the proposed framework is demonstrated experimentally. It is observed that the methodology identifies 350% more testable faults in the ISCAS'85 benchmark C6288 than any existing technique by utilizing only a fraction of the time compared to earlier work.