On Selecting Testable Paths in Scan Designs
Journal of Electronic Testing: Theory and Applications
Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults
Proceedings of the conference on Design, automation and test in Europe - Volume 1
TranGen: a SAT-based ATPG for path-oriented transition faults
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation
Journal of Electronic Testing: Theory and Applications
Fast false path identification based on functional unsensitizability using RTL information
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Techniques to prioritize paths for diagnosis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
Several methods to reduce the run time and memory requirements of a procedure used to efficiently identify untestable path delay faults are proposed in this work. Based on the correlation between the conditions required for sensitizing subpaths in the fan-out-free regions of a circuit, equivalence relations between the subpaths are defined. Equivalence relations are used to reduce the number of subpaths considered in the identification of untestable paths. Dynamic pruning of the potential search space for identifying pairs of subpaths that cannot be sensitized together is used to achieve additional speedup. Results on benchmark circuits show the effectiveness of the proposed methods.