A satisfiability-based test generator for path delay faults in combinational circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Fast identification of untestable delay faults using implications
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
On applying incremental satisfiability to delay fault testing
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver
Proceedings of the 39th annual Design Automation Conference
Test Generation for Path Delay Faults Using Binary Decision Diagrams
IEEE Transactions on Computers
Efficient Identification of Non-Robustly Untestable Path Delay Faults
Proceedings of the IEEE International Test Conference
Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Static logic implication with application to redundancy identification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
An Efficient Method to Identify Untestable Path Delay Faults
ATS '01 Proceedings of the 10th Asian Test Symposium
Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A Novel SAT All-Solutions Solver for Efficient Preimage Computation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Verification of Proofs of Unsatisfiability for CNF Formulas
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Circuit SAT Solver With Signal Correlation Guided Learning
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Enhancing SAT-based equivalence checking with static logic implications
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Classification and identification of nonrobust untestable path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Small-delay defect detection in the presence of process variations
Microelectronics Journal
Functional test generation using efficient property clustering and learning techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics
Journal of Electronic Testing: Theory and Applications
Efficient self-learning techniques for SAT-based test generation
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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In recent years, several Electronic Design Automation (EDA) problems in testing and verification have been formulated as Boolean Satisfiability (SAT) instances due to the development of efficient general-purpose SAT solvers. Problem-specific learning techniques and heuristics can be integrated into the SAT solver to further speed-up the search for a satisfying assignment. In this paper, we target the problem of generating a complete test-suite for the path delay fault (PDF) model. We provide an Incremental Satisfiability framework that learns from (1) static logic implications, (2) segment-specific clauses, and (3) unsatisfiability cores of each untestable partial PDF. These learning techniques improvise the test generation for path delay faults that have common testable and/or untestable segments. The experimental results show that a significant portion of PDFs can be excluded dynamically in the proposed incremental SAT formulation for large benchmark circuits, thus potentially achieving speed-ups for PDF test generation.