Enhancing SAT-based equivalence checking with static logic implications

Authors:
R. Arora;M. S. Hsiao
Affiliations:
Virginia Tech, Blacksburg, VA, USA;Virginia Tech, Blacksburg, VA, USA
Venue:
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Year:
2003

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Abstract

We propose a novel technique to improve SAT-based Combinational Equivalence Checking (CEC) by statically adding meaningful clauses to the CNF formula of the miter circuit. A fast preprocessing quickly builds up the implication graph for the miter circuit under verification, resulting in a large set of direct, indirect and extended backward implications. The non-trivial implications are converted into two-literal clauses and added to the miter CNF database. These added clauses constrain the search space, and provide correlation among the different variables, which enhances the Boolean Constraint Propagation (BCP). Experimental results on ISCAS'85 CEC instances show that with the added clauses, an average speedup of more than 950x was achieved.