Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Advanced verification techniques based on learning
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
Tight integration of combinational verification methods
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Model checking
A machine program for theorem-proving
Communications of the ACM
Circuit-based Boolean Reasoning
Proceedings of the 38th annual Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
A proof engine approach to solving combinational design automation problems
Proceedings of the 39th annual Design Automation Conference
SAT with partial clauses and back-leaps
Proceedings of the 39th annual Design Automation Conference
Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver
Proceedings of the 39th annual Design Automation Conference
Symbolic Model Checking
SAT-Based Image Computation with Application in Reachability Analysis
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Pruning Techniques for the SAT-Based Bounded Model Checking Problem
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
SATO: An Efficient Propositional Prover
CADE-14 Proceedings of the 14th International Conference on Automated Deduction
Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
A novel framework for logic verification in a synthesis environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Refining the SAT decision ordering for bounded model checking
Proceedings of the 41st annual Design Automation Conference
Utilizing don't care states in SAT-based bounded sequential problems
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Incremental deductive & inductive reasoning for SAT-based bounded model checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Enhancing SAT-based equivalence checking with static logic implications
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Verification of large scale nano systems with unreliable nano devices
Nano, quantum and molecular computing
Guiding simulation with increasingly refined abstract traces
Proceedings of the 43rd annual Design Automation Conference
Improved visibility in one-to-many trace concretization
Proceedings of the conference on Design, automation and test in Europe
Verification Techniques for System-Level Design
Verification Techniques for System-Level Design
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Exploiting Target Enlargement and Dynamic Abstraction within Mixed BDD and SAT Invariant Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Under-approximation Heuristics for Grid-based Bounded Model Checking
Electronic Notes in Theoretical Computer Science (ENTCS)
Combining abstraction refinement and SAT-based model checking
TACAS'07 Proceedings of the 13th international conference on Tools and algorithms for the construction and analysis of systems
Learning from Constraints for Formal Property Checking
Journal of Electronic Testing: Theory and Applications
CirCUs: a hybrid satisfiability solver
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
MDG-SAT: an automated methodology for efficient safety checking
International Journal of Critical Computer-Based Systems
SAT-Based verification methods and applications in hardware verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
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Bounded Model Checking (BMC) based on Boolean Satisfiability (SAT) procedures has recently gained popularity as an alternative to BDD-based model checking techniques for finding bugs in large designs. In this paper, we explore the use of learning from BDDs, where learned clauses generated by BDD-based analysis are added to the SAT solver, to supplement its other learning mechanisms. We propose several heuristics for guiding this process, aimed at increasing the usefulness of the learned clauses, while reducing the overheads. We demonstrate the effectiveness of our approach on several industrial designs, where BMC performance is improved and the design can be searched up to a greater depth by use of BDD-based learning.