Utilizing don't care states in SAT-based bounded sequential problems

  • Authors:
  • Sean Safarpour;Görschwin Fey;Andreas Veneris;Rolf Drechsler

  • Affiliations:
  • University of Toronto, Toronto, Canada;Bremen University, Bremen, Germany;University of Toronto, Toronto, Canada;Bremen University, Bremen, Germany

  • Venue:
  • GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
  • Year:
  • 2005

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Abstract

Boolean Satisfiability (SAT) solvers are popular engines used throughout the verification world. Bounded sequential problems such as bounded model checking and bounded sequential equivalence checking rely on fast and robust SAT solvers. In this work, we introduce a technique that improves the performance of the underlying SAT solver for bounded sequential problems by taking advantage of a design's don't care states. We develop cost effective methods of filtering, replicating and applying the don't care states to the original problem thus reducing the search space. Experiments demonstrate the effectiveness of the proposed method on ISCAS'89 benchmarks.