Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Diagnosis and correction of multiple logic design errors in digital circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Implementation and use of SPFDs in optimizing Boolean networks
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Utilizing don't care states in SAT-based bounded sequential problems
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Automating Logic Rectification by Approximate SPFDs
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Logic synthesis for engineering change
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SPFD: A new method to express functional flexibility
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the verification of sequential equivalence
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault diagnosis and logic debugging using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using simulation and satisfiability to compute flexibilities in Boolean networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combinational and sequential logic optimization by redundancy addition and removal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In the digital VLSI cycle, logic transformations are often required to modify the design to meet different synthesis and optimization goals. Logic transformations on sequential circuits are hard to perform due to the vast underlying solution space. This paper proposes an SPFD-based sequential logic transformation methodology to tackle the problem with no sacrifice on performance. It first presents an efficient approach to construct approximate SPFDs (aSPFDs) for sequential circuits. Then, it demonstrates an algorithm using aSPFDs to perform the desirable sequential logic transformations using both combinational and sequential don't cares. Experimental results show the effectiveness and robustness of the approach.