A new method to express functional permissibilities for LUT based FPGAs and its applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Fast post-placement rewiring using easily detectable functional symmetries
Proceedings of the 37th Annual Design Automation Conference
Power and delay reduction via simultaneous logic and placement optimization in FPGAs
DATE '00 Proceedings of the conference on Design, automation and test in Europe
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Logic Synthesis and Verification
The future of logic synthesis and verification
Logic Synthesis and Verification
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Compatible observability don't cares revisited
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A new enhanced SPFD rewiring algorithm
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Topologically constrained logic synthesis
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Resynthesis of multi-level circuits under tight constraints using symbolic optimization
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Implicit enumeration of structural changes in circuit optimization
Proceedings of the 41st annual Design Automation Conference
Theory of wire addition and removal in combinational Boolean networks
Microelectronic Engineering
How much can logic perturbation help from netlist to final routing for FPGAs
Proceedings of the 44th annual Design Automation Conference
Robust window-based multi-node technology-independent logic minimization
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Proceedings of the 47th Design Automation Conference
ECR: a low complexity generalized error cancellation rewiring scheme
Proceedings of the 47th Design Automation Conference
Sequential logic rectifications with approximate SPFDs
Proceedings of the Conference on Design, Automation and Test in Europe
ECR: A Powerful and Low-Complexity Error Cancellation Rewiring Scheme
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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