Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The use of observability and external don't cares for the simplification of multi-level networks
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
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DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
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Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Don't cares and multi-valued logic network minimization
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Compatible observability don't cares revisited
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Optimization of Multi-Valued Multi-Level Networks
ISMVL '02 Proceedings of the 32nd International Symposium on Multiple-Valued Logic
A recursive paradigm to solve Boolean relations
Proceedings of the 41st annual Design Automation Conference
A robust algorithm for approximate compatible observability don't care (CODC) computation
Proceedings of the 41st annual Design Automation Conference
SAT-Based Complete Don't-Care Computation for Network Optimization
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An Approach to Unified Methodology of Combinational Switching Circuits
IEEE Transactions on Computers
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Multi-node optimization using Boolean relations is a powerful approach for network minimization. In this paper, we present an algorithm to perform Boolean relation-based multi-node optimization using a robust, fast and memory efficient algorithm. In particular, we simultaneously optimize two nodes at a time. The robustness of our approach arises from the use of a window-based technique for computing these Boolean relations. Secondly, we perform early quantification during the computation, keeping memory utilization low. Finally, we employ smart heuristics for selecting the node pair to be optimized simultaneously. These features allow the approach to scale well and provide good results for large designs. We perform experiments on a set of large benchmarks and compare our algorithm's performance to a recent SAT-based network optimization technique using complete don't cares. On average, we achieve a 15% reduction in literal count across all the large designs, compared to the complete don't care-based method while maintaining small runtimes and low memory usage.