Improved SAT-based Boolean matching using implicants for LUT-based FPGAs
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Robust window-based multi-node technology-independent logic minimization
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Logic synthesis and circuit customization using extensive external don't-cares
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.00 |
A program called MVSIS has been developed which optimizesmulti-level multi-valued networks (MV networks).We describe what such a network is and the capabilitiescontained in MVSIS. MVSIS is modeled after SIS, whichsynthesizes binary multi-level networks, but the logic networkof MVSIS is such that all variables can be multi-valuedeach with its own range. Included in MVSIS arealmost all the technology-independent transformations ofSIS for combinational and sequential logic synthesis aswell as transformations specific to multi-valued nodes suchas merge, pair decode, encode. MVSIS can readand write BLIF-MV and BLIF files which describe MV-networksand binary networks respectively.