Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
BDD based decomposition of logic functions with application to FPGA synthesis
DAC '93 Proceedings of the 30th international Design Automation Conference
Don't cares in multi-level network optimization
Don't cares in multi-level network optimization
Optimum functional decomposition using encoding
DAC '94 Proceedings of the 31st annual Design Automation Conference
Functional multiple-output decomposition: theory and an implicit algorithm
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Logic decomposition during technology mapping
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
M32: a constructive multilevel logic synthesis system
DAC '98 Proceedings of the 35th annual Design Automation Conference
Implementation and use of SPFDs in optimizing Boolean networks
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Constructive library-aware synthesis using symmetries
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Multi-output functional decomposition with exploitation of don't cares
Proceedings of the conference on Design, automation and test in Europe
Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques
Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques
LSS: a system for production logic synthesis
IBM Journal of Research and Development
Iterative remapping for logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BDD minimization using symmetries
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Understanding metrics in logic synthesis for routability enhancement
Proceedings of the 2003 international workshop on System-level interconnect prediction
A new enhanced constructive decomposition and mapping algorithm
Proceedings of the 40th annual Design Automation Conference
Timing closure for low-FO4 microprocessor design
Proceedings of the 41st annual Design Automation Conference
Implicit enumeration of structural changes in circuit optimization
Proceedings of the 41st annual Design Automation Conference
Detecting support-reducing bound sets using two-cofactor symmetries
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
| Hi-index | 0.00 |
We apply recently introduced constructive multi-level synthesis in the resynthesis loop targeting convergence of industrial designs. The incremental ability of the resynthesis approach allows more predictable circuit implementations while allowing their aggressive optimization. The approach is based on a very general symbolic decomposition template for logic synthesis that uses information-theoretical properties of a function to infer its decomposition patterns (rather than more conventional measures such as literal counts). Using this template the decomposition is done in a Boolean domain unrestricted by the representation of a function, enabling superior implementation choices driven by additional technological constraints. The symbolic optimization is applied in resynthesis of industrial circuits which have tight timing constraints yielding their much improved timing properties.