Physical planning with retiming
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Concurrent flip-flop and repeater insertion for high performance integrated circuits
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Resynthesis of multi-level circuits under tight constraints using symbolic optimization
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Sequential delay budgeting with interconnect prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we discuss timing closure for high performance microprocessor designs. Aggressive cycle time and deep sub-micron technology scaling introduce a myriad of problems that are not present in the ASIC domain. The impact of these problems on floorplanning, placement, clocking and logic synthesis is described. We present ideas and potential solutions for tackling these problems.