Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Verification of synchronous sequential machines based on symbolic execution
Proceedings of the international workshop on Automatic verification methods for finite state systems
BDD based decomposition of logic functions with application to FPGA synthesis
DAC '93 Proceedings of the 30th international Design Automation Conference
Optimum functional decomposition using encoding
DAC '94 Proceedings of the 31st annual Design Automation Conference
The disjunctive decomposition of logic functions
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Graph coloring algorithms for fast evaluation of Curtis decompositions
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Area and search space control for technology mapping
Proceedings of the 37th Annual Design Automation Conference
An algorithm for bi-decomposition of logic functions
Proceedings of the 38th annual Design Automation Conference
Synthesis of Finite State Machines: Functional Optimization
Synthesis of Finite State Machines: Functional Optimization
Simplification of non-deterministic multi-valued networks
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Resynthesis of multi-level circuits under tight constraints using symbolic optimization
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Quasi-algebraic decompositions of switching functions
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Constructive multi-level synthesis by way of functional properties
Constructive multi-level synthesis by way of functional properties
Computing support-minimal subfunctions during functional decomposition
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logic decomposition during technology mapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BDS: a BDD-based logic optimization system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Implicit enumeration of structural changes in circuit optimization
Proceedings of the 41st annual Design Automation Conference
SAT-Based Complete Don't-Care Computation for Network Optimization
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Detecting support-reducing bound sets using two-cofactor symmetries
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Reducing structural bias in technology mapping
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits
Proceedings of the conference on Design, automation and test in Europe
FPGA area reduction by multi-output function based sequential resynthesis
Proceedings of the 45th annual Design Automation Conference
Boolean factoring and decomposition of logic networks
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Robust FPGA resynthesis based on fault-tolerant Boolean matching
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Global delay optimization using structural choices
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Delay optimization using SOP balancing
Proceedings of the International Conference on Computer-Aided Design
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Structuring and mapping of a Boolean function is an important problem in the design of complex integrated circuits. Library-aware constructive decomposition offers a solution to this problem. This paper proposes novel techniques to improve the quality and runtime of constructive decomposition. The improvements are effective both in the stand-alone mapping procedure and in the context of re-synthesis applied to a mapped multi-level network. Experiments with public and proprietary benchmarks show promising results.