DAGON: technology binding and local optimization by DAG matching
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A survey of Boolean matching techniques for library binding
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Boolean matching for large libraries
DAC '98 Proceedings of the 35th annual Design Automation Conference
Delay-optimal technology mapping by DAG covering
DAC '98 Proceedings of the 35th annual Design Automation Conference
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DATE '99 Proceedings of the conference on Design, automation and test in Europe
Constructive library-aware synthesis using symmetries
DATE '00 Proceedings of the conference on Design, automation and test in Europe
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Efficent Boolean Matching Algorithm for Cell Libraries
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
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DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Dynamic transition relation simplification for bounded property checking
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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DAG-aware AIG rewriting a fresh look at combinational logic synthesis
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Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Improvements to combinational equivalence checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
WireMap: FPGA technology mapping for improved routability
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
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Proceedings of the 45th annual Design Automation Conference
Boolean factoring and decomposition of logic networks
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
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Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Recording synthesis history for sequential verification
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Timing-driven N-way decomposition
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ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
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CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
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DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Technology mapping based on DAG-covering suffers from the problem of structural bias: the structure of the mapped netlist depends strongly on the subject graph. In this paper we present a new mapper aimed at mitigating structural bias. It is based on a simplified cut-based Boolean matching algorithm, and using the speed afforded by this simplification we explore two ideas to reduce structural bias. The first, called lossless synthesis, leverages recent advances in structure-based combinational equivalence checking to combine the different networks seen during technology independent synthesis into a single network with choices in a scalable manner. We show how cut based mapping extends naturally to handle such networks with choices. The second idea is to combine several library gates into a single gate (called a supergate) in order to make the matching process less local. We show how supergates help address the structural bias problem, and how they fit naturally into the cut-based Boolean matching scheme. An implementation based on these ideas significantly outperforms state-of-the-art mappers in terms of delay, area and run-time on academic and industrial benchmarks.