A new retiming-based technology mapping algorithm for LUT-based FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Cut ranking and pruning: enabling a general and efficient FPGA mapping solution
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Improvements to technology mapping for LUT-based FPGAs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Reducing structural bias in technology mapping
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Building a better Boolean matcher and symmetry detector
Proceedings of the conference on Design, automation and test in Europe: Proceedings
DAG-aware AIG rewriting a fresh look at combinational logic synthesis
Proceedings of the 43rd annual Design Automation Conference
FPGA logic synthesis using quantified boolean satisfiability
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
FPGA technology mapping with encoded libraries andstaged priority cuts
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Boolean factoring and decomposition of logic networks
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Design and synthesis of programmable logic block with mixed LUT and macrogate
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
KL-cuts: a new approach for logic synthesis targeting multiple output blocks
Proceedings of the Conference on Design, Automation and Test in Europe
FPGA technology mapping with encoded libraries and staged priority cuts
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Enumeration of bounded size cuts is an important step in several logic synthesis algorithms such as technology mapping and re-writing. The standard algorithm does not scale beyond 6 or 7 inputs because it enumerates all cuts and there are too many of them. We address the enumeration problem by introducing the notion of cut factorization. In cut factorization, one enumerates global and local cuts (collectively called the factor cuts) of the network, and uses these to generate other cuts. Depending on how global and local cuts are defined, one obtains different factorization schemes. In the first scheme, complete factorization, it is possible to generate any cut from factor cuts. However, complete factorization is expensive though less expensive than exhaustive enumeration. In the second scheme, partial factorization, there is no guarantee of generating all cuts from factor cuts. However, it is much faster, and produces good results. In this paper we also present two applications of factor cuts: LUT mapping and macrocell mapping. In LUT mapping, we find that considering only factor cuts guarantees depth optimality for most nodes in the network. For the remaining nodes, other cuts need to be generated from factor cuts and examined. In macrocell mapping, we focus on a particular 9-input macrocell, and use factor cuts as a heuristic method to improve depth by reducing structural bias. Factor cuts are used to map the macrocell as a whole whenever possible instead of mapping its parts separately. In this context factor cuts enable a new quality-run-time tradeoff between mapping parts of the macrocell separately (poor quality), and mapping using all 9-input cuts (long run-time).