Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Cut ranking and pruning: enabling a general and efficient FPGA mapping solution
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
A Fast and Exact Cell Matching Method for MUX-Based FPGA Technology Mapping
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
The Stratix II logic and routing architecture
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
A new canonical form for fast boolean matching in logic synthesis and verification
Proceedings of the 42nd annual Design Automation Conference
FPGA technology mapping: a study of optimality
Proceedings of the 42nd annual Design Automation Conference
DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Building a better Boolean matcher and symmetry detector
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Efficient SAT-based Boolean matching for FPGA technology mapping
Proceedings of the 43rd annual Design Automation Conference
Improved SAT-based Boolean matching using implicants for LUT-based FPGAs
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Combinational and sequential mapping with priority cuts
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
WireMap: FPGA technology mapping for improved routability
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improvements to Technology Mapping for LUT-Based FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Building a faster boolean matcher using bloom filter
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
FPGA technology mapping with encoded libraries and staged priority cuts
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Technology mapping is an important step in the FPGA CAD flow in which a network of simple gates is converted into a network of logic blocks. We consider enhancements to a traditional LUT-based mapping algorithm for an FPGA comprised of logic blocks which implement only a subset of functions of up to k variables--specifically, the logic block is a partial LUT, but it possesses more inputs than typical LUTs. Numerical results are presented to demonstrate the efficacy of our proposed techniques using real circuits mapped to a commercial FPGA architecture.