How much can logic perturbation help from netlist to final routing for FPGAs
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Mapping for better than worst-case delays in LUT-based FPGA designs
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Area recovery under depth constraint by cut substitution for technology mapping for LUT-based FPGAs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
FPGA technology mapping with encoded libraries andstaged priority cuts
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Physical optimization for FPGAs using post-placement topology rewriting
Proceedings of the 2009 international symposium on Physical design
On K-LUT based FPGA optimum delay and optimal area mapping
MACMESE'08 Proceedings of the 10th WSEAS international conference on Mathematical and computational methods in science and engineering
Design and synthesis of programmable logic block with mixed LUT and macrogate
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Dynamic data folding with parameterizable FPGA configurations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
FPGA technology mapping with encoded libraries and staged priority cuts
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter cones
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
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In this paper, an iterative technology-mapping tool called IMap is presented. It supports depth-oriented (area is a secondary objective), area-oriented (depth is a secondary objective), and duplication-free mapping modes. The edge-delay model (as opposed to the more commonly used unit-delay model) is used throughout. Two new heuristics are used to obtain area reductions over previously published methods. The first heuristic predicts the effects of various mapping decisions on the area of the final solution, and the second heuristic bounds the depth of the mapping solution at each node. In depth-oriented mode, when targeting five lookup tables (LUTs), IMap obtains depth optimal solutions that are 44.4%, 19.4%, and 5% smaller than those produced by FlowMap, CutMap, and DAOMap, respectively. Targeting the same LUT size in area-oriented mode, IMap obtains solutions that are 17.5% and 9.4% smaller than those produced by duplication-free mapping and ZMap, respectively. IMap is also shown to be highly efficient. Runtime improvements of between 2.3times and 82times are obtained over existing algorithms when targeting five LUTs. Area and runtime results comparing IMap to the other mappers when targeting four and six LUTs are also presented