Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Cut ranking and pruning: enabling a general and efficient FPGA mapping solution
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Using logic duplication to improve performance in FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Timing optimization of FPGA placements by logic replication
Proceedings of the 40th annual Design Automation Conference
Simultaneous timing-driven placement and duplication
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
A new canonical form for fast boolean matching in logic synthesis and verification
Proceedings of the 42nd annual Design Automation Conference
FPGA technology mapping: a study of optimality
Proceedings of the 42nd annual Design Automation Conference
DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Building a better Boolean matcher and symmetry detector
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Efficient SAT-based Boolean matching for FPGA technology mapping
Proceedings of the 43rd annual Design Automation Conference
DAG-aware AIG rewriting a fresh look at combinational logic synthesis
Proceedings of the 43rd annual Design Automation Conference
Improved SAT-based Boolean matching using implicants for LUT-based FPGAs
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
An area-efficient timing closure technique for FPGAs using Shannon's expansion
Integration, the VLSI Journal
How much can logic perturbation help from netlist to final routing for FPGAs
Proceedings of the 44th annual Design Automation Conference
Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A framework for layout-level logic restructuring
Proceedings of the 2008 international symposium on Physical design
Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improvements to Technology Mapping for LUT-Based FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Due to poor correlations between pre- and post-placement timing analysis, many post-placement optimization strategies have been proposed for the FPGA CAD flow to improve circuit performance. Typically, these methods depend on logic duplication or decomposition methods combine together with incremental placement. Circuit rewriting has proven to be a useful optimization strategy, but is typically applied during the technology mapping step of the FPGA CAD flow. While beneficial, rewriting either before or after technology mapping must rely on circuit depth rather than post-placement delays for timing optimization. In this paper, we show that circuit rewriting can also be used as a post-placement optimization for FPGAs. We present a post-placement optimization based on circuit rewriting which is guided by post-placement timing analysis. We replace, or rewrite, cones of logic on critical paths to improve the timing performance of a circuit. Our method is integrated with incremental placement to ensure valid placements and to guarantee that our timing analysis remains accurate throughout our proposed rewriting method. The key to our method is the ability to quickly determine if an alternative topology of LUTs is suitable for the replacement of a cone of logic on a critical path. We have implemented our proposed method in a commercial FPGA CAD flow. Experimental results demonstrate that the application of our rewriting algorithm can improve the routed timing performance of a design by 3.1% on average and by as much as 37.9% when applied to a set of 136 industrial designs.