A methodology and algorithms for post-placement delay optimization
DAC '94 Proceedings of the 31st annual Design Automation Conference
Post-layout logic restructuring for performance optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
Timing driven placement in interaction with netlist transformations
Proceedings of the 1997 international symposium on Physical design
Integrated retiming and placement for field programmable gate arrays
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Incremental placement for layout driven optimizations on FPGAs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A framework for layout-level logic restructuring
Proceedings of the 2008 international symposium on Physical design
Physical optimization for FPGAs using post-placement topology rewriting
Proceedings of the 2009 international symposium on Physical design
Fast and effective placement and routing directed high-level synthesis for FPGAs
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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This paper presents a technique to optimize the speed performance of circuits implemented in FPGAs. After synthesis, technology mapping and placement are complete, we apply Shannon's expansion to the most critical sections of the circuit. This approach allows us to precompute the values of functions that depend on late-arriving critical signals and use a multiplexer to quickly select the appropriate value when the signal arrives. Any new logic elements created by this technique are incrementally placed in a minimally disruptive fashion to ensure convergence between the circuit optimization and the netlist placement. Experimental results show that this technique can improve the performance of circuits by 11% on average, and up to 30% in some cases.