Chortle-crf: Fast technology mapping for lookup table-based FPGAs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Delay-optimal technology mapping by DAG covering
DAC '98 Proceedings of the 35th annual Design Automation Conference
Timing-driven placement for FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Timing driven gate duplication: complexity issues and algorithms
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Placement-driven technology mapping for LUT-based FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Using logic duplication to improve performance in FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization
IEEE Design & Test
Timing optimization of FPGA placements by logic replication
Proceedings of the 40th annual Design Automation Conference
Incremental physical resynthesis for timing optimization
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Simultaneous timing-driven placement and duplication
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Techniques for improved placement-coupled logic replication
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
An area-efficient timing closure technique for FPGAs using Shannon's expansion
Integration, the VLSI Journal
Logic decomposition during technology mapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Approach to Placement-Coupled Logic Replication
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Physical optimization for FPGAs using post-placement topology rewriting
Proceedings of the 2009 international symposium on Physical design
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It is well known that optimizations made by traditional logic synthesis tools often correlate poorly with post-layout performance; this is largely a result of interconnect effects only visible after layout. As a result, several attempts at physically aware logic synthesis have been made (e.g.,[2], [9], [14], [4], [7], [12], [16], [15]). In this paper a corrective methodology is proposed for timing-driven logic restructuring at the placement level; the approach currently focuses on LUT-based FPGAs. Driven by placement level static timing analysis, the method induces relatively large, timing-critical fan-in trees via (temporary) replication as in [9]. Such trees are then reimplemented where the degrees of freedom include functional decomposition of LUTs, subject graph covering/mapping, and physical embedding. A dynamic programming algorithm optimizes over all of these freedoms simultaneously. All simple disjoint decompositions (i.e., Ashenhurst style) are encoded in the subject tree/graph using choice nodes similar to those in [11]. At the same time, because embedding is done simultaneously, interconnect delay is directly taken into account We have implemented the framework and in many cases we were able to approach a fixed flip-flop lower-bound on achievable clock period. Promising experimental results are reported with average 14.8% (up to 37.4%) clock period reduction compared with the timing-driven placement from VPR [13] and average 6.6% (upto 17%) reduction compared with the basic fan-in tree embedder from [9].