RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Efficient circuit clustering for area and power reduction in FPGAs
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
A synthesis oriented omniscient manual editor
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Incremental physical resynthesis for timing optimization
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Efficient static timing analysis and applications using edge masks
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Techniques for improved placement-coupled logic replication
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Architecture-specific packing for virtex-5 FPGAs
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
A framework for layout-level logic restructuring
Proceedings of the 2008 international symposium on Physical design
On the trade-off between power and flexibility of FPGA clock networks
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Physical optimization for FPGAs using post-placement topology rewriting
Proceedings of the 2009 international symposium on Physical design
Packing Techniques for Virtex-5 FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
| Hi-index | 0.00 |
The purpose of this paper is to introduce a modified packing and placement algorithm for FPGAs that utilizes logic duplication to improve performance. The modified packing algorithm was designed to leave unused basic logic elements (BLEs) in timing critical clusters, to allow potential targets for logic duplication. The modified placement algorithm consists of a new stage after placement in which logic duplication is performed to shorten the length of the critical path. In this paper, we show that in a representative FPGA architecture using .18 mm technology, the length of the final critical path can be reduced by an average of 14.1%. Approximately half of this gain comes directly from the changes to the packing algorithm while the other half comes from the logic duplication performed during placement.