Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Efficient circuit clustering for area and power reduction in FPGAs
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Using logic duplication to improve performance in FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
On the Interaction Between Power-Aware FPGA CAD Algorithms
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Delay optimal low-power circuit clustering for FPGAs with dual supply voltages
Proceedings of the 2004 international symposium on Low power electronics and design
LAP: a logic activity packing methodology for leakage power-tolerant FPGAs
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Optimal simultaneous mapping and clustering for FPGA delay optimization
Proceedings of the 43rd annual Design Automation Conference
RQL: global placement via relaxed quadratic spreading and linearization
Proceedings of the 44th annual Design Automation Conference
Architecture-specific packing for virtex-5 FPGAs
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
WireMap: FPGA technology mapping for improved routability
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Measuring the Gap Between FPGAs and ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast and effective placement and routing directed high-level synthesis for FPGAs
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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Packing is a key step in the FPGA tool flow that straddles the boundaries between synthesis, technology mapping and placement. Packing strongly influences circuit speed, density, and power, and in this article, we consider packing in the commercial FPGA context and examine the area and performance trade-offs associated with packing in a state-of-the-art FPGA---the Xilinx® VirtexTM-5 FPGA. In addition to look-up-table (LUT)-based logic blocks, modern FPGAs also contain large IP blocks. We discuss packing techniques for both types of blocks. Virtex-5 logic blocks contain dual-output 6-input LUTs. Such LUTs can implement any single logic function of up to 6 inputs, or any two logic functions requiring no more than 5 distinct inputs. The second LUT output has reduced speed, and therefore, must be used judiciously. We present techniques for dual-output LUT packing that lead to improved area-efficiency, with minimal performance degradation. We then describe packing techniques for large IP blocks, namely, block RAMs and DSPs. We pack circuits into the large blocks in a way that leverages the unique block RAM and DSP layout/architecture in Virtex-5, achieving significantly improved design performance.