Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Efficient circuit clustering for area and power reduction in FPGAs
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Using logic duplication to improve performance in FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Delay optimal low-power circuit clustering for FPGAs with dual supply voltages
Proceedings of the 2004 international symposium on Low power electronics and design
LAP: a logic activity packing methodology for leakage power-tolerant FPGAs
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Optimal simultaneous mapping and clustering for FPGA delay optimization
Proceedings of the 43rd annual Design Automation Conference
RQL: global placement via relaxed quadratic spreading and linearization
Proceedings of the 44th annual Design Automation Conference
Measuring the Gap Between FPGAs and ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Clock power reduction for virtex-5 FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Packing Techniques for Virtex-5 FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Proceedings of the Conference on Design, Automation and Test in Europe
Fault-tolerant resynthesis with dual-output LUTs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
In-place decomposition for robustness in FPGA
Proceedings of the International Conference on Computer-Aided Design
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We consider packing in the commercial FPGA context and examine the speed, performance and power trade-offs associated with packing in a state-of-the art FPGA -- the Xilinx Virtex-5 FPGA. Two aspects of packing are discussed: 1)packing for general logic blocks, and 2 packing for large IP blocks. Virtex-5 logic blocks contain dual-output 6-input look-up-tables (LUTs). Such LUTs can implement any single logic function requiring no more than 6 inputs, or any two logic functions requiring no more than 5 distinct inputs. The second LUT output is associated with slower speed, and therefore, must be used judiciously. We present placement-based techniques for dual-output LUT packing that lead to improved area-efficiency and power, with minimal performance degradation. We then move on to address packing for large IP blocks, specifically, block RAMs and DSPs. We present a packing optimization that is widely applicable in DSP designs that leads to significantly improved design performance