PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Emerald: an architecture-driven tool compiler for FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Efficient circuit clustering for area and power reduction in FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
RaPiD - Reconfigurable Pipelined Datapath
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Design of Interconnection Networks for Programmable Logic
Design of Interconnection Networks for Programmable Logic
Improvements to technology mapping for LUT-based FPGAs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Optimal simultaneous mapping and clustering for FPGA delay optimization
Proceedings of the 43rd annual Design Automation Conference
Combinational and sequential mapping with priority cuts
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Architecture-specific packing for virtex-5 FPGAs
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
WireMap: FPGA technology mapping for improved routability
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Fundamentals of Digital Logic with Verilog Design
Fundamentals of Digital Logic with Verilog Design
CGADL: an architecture description language for coarse-grained reconfigurable arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Floating-point FPGA: architecture and modeling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research
FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
Scalable Synthesis and Clustering Techniques Using Decision Diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Ultra-fine grain FPGAs: A granularity study
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Making wide-issue VLIW processors viable on FPGAs
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
The VTR project: architecture and CAD for FPGAs from verilog to routing
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter cones
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
A novel FPGA design framework with VLSI post-routing performance analysis (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
An Analytical Model for Evaluating Static Power of Homogeneous FPGA Architectures
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Towards interconnect-adaptive packing for FPGAs
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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The development of future FPGA fabrics with more sophisticated and complex logic blocks requires a new CAD flow that permits the expression of that complexity and the ability to synthesize to it. In this paper, we present a new logic block description language that can depict complex intra-block interconnect, hierarchy and modes of operation. These features are necessary to support modern and future FPGA complex soft logic blocks, memory and hard blocks. The key part of the CAD flow associated with this complexity is the packer, which takes the logical atomic pieces of the complex blocks and groups them into whole physical entities. We present an area-driven generic packing tool that can pack the logical atoms into any heterogeneous FPGA described in the new language, including many different kinds of soft and hard logic blocks. We gauge its area quality by comparing the results achieved with a lower bound on the number of blocks required, and then illustrate its explorative capability in two ways: on fracturable LUT soft logic architectures, and on hard block memory architectures. The new infrastructure attaches to a flow that begins with a Verilog front-end, permitting the use of benchmarks that are significantly larger than the usual ones, and can target heterogenous FPGAs.