Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Roadmap for 22nm and beyond (Invited Paper)
Microelectronic Engineering
Novel library of logic gates with ambipolar CNTFETs: opportunities for multi-level logic synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Matrix Nanodevice-Based Logic Architectures and Associated Functional Mapping Method
ACM Journal on Emerging Technologies in Computing Systems (JETC)
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
High-performance carbon nanotube field-effect transistor with tunable polarities
IEEE Transactions on Nanotechnology
Performance Benefits of Monolithically Stacked 3-D FPGA
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we investigate the opportunity to use ultra-fine grain logic cells to design reconfigurable circuits. We use ultra-fine grain computation cells, built with only 7 Double-Gate Carbon Nanotubes FETs, and we arrange them into regular matrices with a fixed and incomplete interconnection pattern, in order to minimize the reconfigurable interconnection overhead. We subsequently organize them into Field-Programmable Gate Arrays (FPGAs) suited to ultra-fine grain reconfigurability. To assess this architectural scheme in an efficient and objective manner, we propose a complete benchmarking tool flow, which enables the optimization of the specific interconnection topologies. We finally perform the evaluation with widely used circuit benchmarks, and we show that the matrices have an optimal size of 3 by 3, while the ultra-fine grain FPGA demonstrated an area saving of up to 62% with respect to the CMOS LUT FPGA counterpart.