Modeling and analysis of circuit performance of ballistic CNFET
Proceedings of the 43rd annual Design Automation Conference
Novel CNTFET-based reconfigurable logic gate design
Proceedings of the 44th annual Design Automation Conference
Prospect of ballistic CNFET in high performance applications: Modeling and analysis
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Proceedings of the 45th annual Design Automation Conference
Analysis of universal logic gates using carbon nanotube field effect transistor
Proceedings of the International Conference and Workshop on Emerging Trends in Technology
Power consumption of logic circuits in ambipolar carbon nanotube technology
Proceedings of the Conference on Design, Automation and Test in Europe
Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Novel library of logic gates with ambipolar CNTFETs: opportunities for multi-level logic synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Matrix Nanodevice-Based Logic Architectures and Associated Functional Mapping Method
ACM Journal on Emerging Technologies in Computing Systems (JETC)
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
Universal logic modules based on double-gate carbon nanotube transistors
Proceedings of the 48th Design Automation Conference
A model for carbon nanotube FETs in the ballistic limit
Microelectronics Journal
Design and analysis of a new carbon nanotube full adder cell
Journal of Nanomaterials
Ultra-fine grain FPGAs: A granularity study
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
LSSC'05 Proceedings of the 5th international conference on Large-Scale Scientific Computing
Ambipolar double-gate FETs for the design of compact logic structures
Proceedings of the great lakes symposium on VLSI
Journal of Nanomaterials - Special issue on Nanocrystals for Electronic and Optoelectronic Applications
Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors
Proceedings of the 49th Annual Design Automation Conference
Ultra low power dual-gate 6T and 8T stack forced CNFET SRAM cells
Microelectronics Journal
Proceedings of the Conference on Design, Automation and Test in Europe
Biconditional BDD: a novel canonical BDD for logic synthesis targeting XOR-rich circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Towards structured ASICs using polarity-tunable Si nanowire transistors
Proceedings of the 50th Annual Design Automation Conference
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State-of-the-art carbon nanotube field-effect transistors (CNFETs) behave as Schottky-barrier-modulated transistors. It is known that vertical scaling of the gate oxide significantly improves the performance of these devices. However, decreasing the oxide thickness also results in pronounced ambipolar transistor characteristics and increased drain leakage currents. Using a novel device concept, we have fabricated high-performance enhancement-mode CNFETs exhibiting n- or p-type unipolar behavior, tunable by electrostatic and/or chemical doping, with excellent OFF-state performance and a steep subthreshold swing (S=63 mV/dec). The device design allows for aggressive oxide thickness and gate-length scaling while maintaining the desired device characteristics.