Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Double-Gate SOI Devices for Low-Power and High-Performance Applications
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Reducing transistor count in clocked standard cells with ambipolar double-gate FETs
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Novel library of logic gates with ambipolar CNTFETs: opportunities for multi-level logic synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Ambipolar double-gate FET binary-decision- diagram (Am-BDD) for reconfigurable logic cells
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
High-performance carbon nanotube field-effect transistor with tunable polarities
IEEE Transactions on Nanotechnology
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We present in this paper a circuit design approach to achieve compact logic circuits with ambipolar double-gate devices, using the in-field controllability of such devices. The approach is demonstrated for complementary static logic design style. We apply this approach in a case study focused on Double Gate Carbon Nanotube FET (DG-CNTFET) technology and show that, with respect to conventional CMOS-like static logic structures and for comparable power consumption, time delay and integration density can both be improved by a factor of 1.5x and 2x, respectively. Compared with a predictive model for 16nm CMOS technology, the gates built according to the design approach described in this work and based on DG-CNTFET offer a gain of 30% concerning Power-Delay-Product (PDP).