Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Minimizing ROBDD Sizes of Incompletely Specified Boolean Functions by Exploiting Strong Symmetries
EDTC '97 Proceedings of the 1997 European conference on Design and Test
QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits
ISMVL '06 Proceedings of the 36th International Symposium on Multiple-Valued Logic
IEEE Transactions on Computers
Reducing transistor count in clocked standard cells with ambipolar double-gate FETs
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Novel library of logic gates with ambipolar CNTFETs: opportunities for multi-level logic synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Ambipolar double-gate FETs for the design of compact logic structures
Proceedings of the great lakes symposium on VLSI
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A novel Ambipolar Binary Decision Diagram (Am-BDD) is proposed in this paper, to adapt this logic synthesis and verification technique to logic built with ambipolar devices. We demonstrate how this method enables us to build DG-CNTFET-based n-input reconfigurable cells based on pass-transistor-logic obtained from Am-BDDs. We also show how specific correlations between configuration signals can lead to a minimization of their total number. Using the Am-BDD technique, we designed a reconfigurable 2-input cell capable of achieving 16 functions and demonstrating a significant reduction in power consumption (6x) with a reduced worst-case time delay when compared to a manually designed reconfigurable 2-input dynamic logic cell DRLC-7T.