Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Scaling of stack effect and its application for leakage reduction
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Double-gate SOI devices for low-power and high-performance applications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Ambipolar double-gate FETs for the design of compact logic structures
Proceedings of the great lakes symposium on VLSI
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In this paper we model (numerically and analytically) and analyze sub-threshold, gate-to-channel tunneling, and edge direct tunneling leakage in Double Gate (DG) devices. We compare the leakage of different DG structures, namely, doped body symmetric device with polysilicon gates, intrinsic body symmetric device with metal gates and intrinsic body asymmetric device with different front and back gate material. It is observed that, use of (near-mid-gap) metal gate and intrinsic body devices significantly reduces both the total leakage and its sensitivity to parametric variations in DG circuits