Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Skewed CMOS: noise-tolerant high-performance low-power static circuit family
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FinFET SRAM " Device and Circuit Design Considerations
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Nanoscale CMOS circuit leakage power reduction by double-gate device
Proceedings of the 2004 international symposium on Low power electronics and design
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
High-speed low-power FinFET based domino logic
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Leakage-delay tradeoff in FinFET logic circuits: a comparative analysis with bulk technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Double-gate (DG) transistors have emerged as promising devices for nano-scale circuits due to their better scalability compared to bulk CMOS. Among the various types of DG devices, quasi-planar SOI FinFETs are easier to manufacture compared to planar double-gate devices. DG devices with independent gates (separate contacts to back and front gates) have recently been developed. DG devices with symmetric and asymmetric gates have also been demonstrated. Such device options have direct implications at the circuit level. Independent control of front and back gate in DG devices can be effectively used to improve performance and reduce power in sub-50nm circuits. Independent gate control can be used to merge parallel transistors in noncritical paths. This results in reduction in the effective switching capacitance and hence power dissipation. We show a variety of circuits in logic and memory that can benefit from independent gate operation of DG devices. As examples, we show the benefit of independent gate operation in circuits such as dynamic logic circuits, Schmitt triggers, sense amplifiers, and SRAM cells. In addition to independent gate option, we also investigate the usefulness of asymmetric devices and the impact of width quantization and process variations on circuit design.