High-speed low-power FinFET based domino logic

Authors:
Seid Hadi Rasouli;Hanpei Koike;Kaustav Banerjee
Affiliations:
University of California, Santa Barbara;Nanoelectronics Research Institute, Tsukuba, Ibaraki, Japan;University of California, Santa Barbara
Venue:
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Year:
2009

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Abstract

This paper introduces a novel FinFET based domino logic, which exploits the exclusive property of the FinFET device (capacitive coupling between front-gate and back-gate in a four-terminal (4T) FinFET) to simultaneously achieve higher performance and lower power consumption. Using a new implementation of the resistive gate, the keeper device is made weaker at the beginning of the evaluation phase to reduce its contention with the pull-down network, but gradually becomes stronger to provide high noise margin. The strength of the keeper device is controlled by the differential gate voltage, which guarantees low gate-source voltage at the beginning of the evaluation phase and high gate-source voltage during rest of the time.