ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Low swing dual threshold voltage domino logic
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Circuit Design Techniques for a Gigahertz Integer Microprocessor
ICCD '98 Proceedings of the International Conference on Computer Design
Sleep switch dual threshold voltage domino logic with reduced standby leakage current
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sleep switch dual threshold voltage domino logic with reduced standby leakage current
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Clock delayed domino logic with efficient variable threshold voltage keeper
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PMOS-only sleep switch dual-threshold voltage domino logic in sub-65-nm CMOS technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-speed low-power FinFET based domino logic
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
FinFET domino logic with independent gate keepers
Microelectronics Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Adaptive keeper design for dynamic logic circuits using rate sensing technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low power dynamic logic circuit design using a pseudo dynamic buffer
Integration, the VLSI Journal
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A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The variable threshold voltage keeper circuit technique enhances circuit evaluation speed by up to 60% while reducing power dissipation by 35% as compared to a standard domino (SD) logic circuit. The keeper size can be increased with the proposed technique while preserving the same delay or power characteristics as compared to a SD circuit. The proposed domino logic circuit technique offers 14% higher noise immunity as compared to a SD circuit with the same evaluation delay characteristics. Forward body biasing the keeper transistor is also proposed for improved noise immunity as compared to a SD circuit with the same keeper size. It is shown that by applying forward and reverse body biased keeper circuit techniques, the noise immunity and evaluation speed of domino logic circuits are simultaneously enhanced.