“Timing closure by design,” a high frequency microprocessor design methodology
Proceedings of the 37th Annual Design Automation Conference
A fast hybrid carry-lookahead/carry-select adder design
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Low swing dual threshold voltage domino logic
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Statistical clock skew modeling with data delay variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells
Journal of VLSI Signal Processing Systems
IEEE Micro
Model Checking the IBM Gigahertz Processor: An Abstraction Algorithm for High-Performance Netlists
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Verification of Delayed-Reset Domino Circuits Using ATACS
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Critical Path Identification and Delay Tests of Dynamic Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
The Use of Pre-Evaluation Phase in Dynamic CMOS Logic
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Limited switch dynamic logic circuits for high-speed low-power circuit design
IBM Journal of Research and Development
Custom circuit design as a driver of microprocessor performance
IBM Journal of Research and Development
IJCNN'09 Proceedings of the 2009 international joint conference on Neural Networks
Domino logic with variable threshold voltage keeper
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low power dynamic logic circuit design using a pseudo dynamic buffer
Integration, the VLSI Journal
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Using highly optimized, custom circuits and fast dynamic array control structures, a small team of designers at the IBM Austin Research Laboratory has developed a one gigahertz microprocessor. This paper describes the custom datapath circuit technology employed in this design. Particular attention was paid in the design process to the trade-off between performance and noise-margins. To achieve the low circuit latencies, highly-optimized and noise-characterized delayed-reset domino circuits were employed in the datapath elements of the gigahertz design.